Electric fuse circuits haven been implemented which program a fuse element by feeding or not feeding a current through the fuse circuit to fuse or not fuse the fuse element. The electric fuse circuit is widely used in semiconductor integrated circuits (LSI) such as trimming program devices for high-frequency semiconductor devices. The conventional electric fuse circuit is made up of electric fuse elements formed of polysilicon and bipolar transistors each feeding a current required to fuse the corresponding electric fuse element. The bipolar transistor is used to feed a large current of about 1 A (Ampere) to fuse the corresponding electric fuse element.
In recent years, in the field of semiconductor integrated circuits, a technique has been developed which forms a silicide layer on a polysilicon layer to reduce the resistance of a gate electrode. Thus, utilizing the technique, an electric fuse element has been developed which has the polysilicon layer and the silicide layer formed over the polysilicon layer such that the resistance is small before the silicide layer is fused and increases when a current is fed to fuse the silicide layer (see U.S. Pat. No. 5,708,291A).
In the electric fuse element, an instantaneous carrying current required to fuse the silicide layer is 10 to 30 mA (milliamperes) for a 130- or 90-nm process generation.
When the electric fuse element utilizing the silicide is used for the trimming program device for the high-frequency semiconductor device or the like, four to eight electric fuse elements are mounted on one chip. Thus, an existing general-purpose tester can be used to fuse all the electric fuse elements at a time.
Furthermore, a metal fuse has been mounted, as a fuse element for redundancy relief, on a RAM in a system LSI such as a DRAM or a SRAM. The electric fuse element utilizing the silicide may be used in place of the metal fuse. However, this technique poses the following problems.
First, 500 to 1,000 fuse elements for RAM redundancy relief are mounted on each chip. Thus, an instantaneous carrying current of about 10 to 30 A is required to fuse the 1,000 electric fuse elements at a time. It is difficult for the existing general-purpose tester to concentrate a current of 10 to 30 A inside an LSI chip, resulting in the need for a dedicated tester. Furthermore, if for example, 1,000 independent electric fuse circuits are mounted in a system LSI and electric fuse elements are sequentially programmed one by one, a large number of control terminals are required. For example, if each circuit has four control terminals, 4,000 control terminals are required but cannot be mounted in the system LSI.
To solve these problems, an electric fuse circuit described below has been proposed (see US 2006/0158920A1). FIG. 11 is a circuit diagram showing the configuration of a conventional electric fuse circuit. As shown in FIG. 11, the electric fuse circuit is composed of a plurality of (n) electric fuse cores 400 and a program shift register block 200 having a plurality of (n) stages.
The electric fuse core 400 has one electric fuse element 401. When a program data signal FBmTi (i=1 to n) is at a High level (hereinafter referred to as an H level), the electric fuse element 401 is set to a fused state while a program enable signal PBmTi (i=1 to n) from the program shift register block 200 is at the H level.
Each stage of the program shift register block 200 generates the program enable signal PmTi (i=1 to n) having a one pulse waveform and sequentially switching to the H level starting at the first stage. The program shift register block 200 inputs the program enable signal PBmTi to each of the first- to nth-stage electric fuse cores 400.
The conventional electric fuse circuit will be described in further detail. As shown in FIG. 11, the electric fuse core 400 comprises the electric fuse element 401, an NMOS transistor 402, and an AND circuit 403 having two input terminals.
One end of the electric fuse element 401 is connected to a power source VDDHE (about 3.3 V), whereas the other end is connected to a drain of the NMOS transistor 402. The NMOS transistor 402 is connected in series with the electric fuse element 401 and has a source connected to a ground terminal. The AND circuit 403 calculates the logical product of the program data signal FBmTi (i=1 to n), input to one of the input terminals, and the program enable signal PBmTi (i=1 to n), input to the other input terminal. The AND circuit 403 then inputs the calculation result, a program signal INmTi (i=1 to n), to a gate of the NMOS transistor 402.
The program shift register block 200 comprises n shift registers (PSR) 201. The n shift registers 201 are serially connected together so that a program control signal FPGI is input to the first stage and so that for the second to nth stages, a signal generated in the stage preceding each stage is input to the latter stage. Furthermore, a program clock signal PCK is input in common to all of the first- to nth-stage shift registers 201. Moreover, the program enable signals PBmTi (i=1 to n) generated by the n shift registers 201 in the program shift register block 200 are input to the first- to nth-stage electric fuse cores 400, respectively.
The specific circuit configuration of the shift register 201 will be described with reference to FIG. 12. FIG. 12 is a circuit diagram showing the configuration of the shift register 201.
As shown in FIG. 12, the shift register 201 comprises two CMOS gate circuits 202 and 205, two inverter circuits 203 and 206, and two tri-state inverter circuits 204 and 207.
The first CMOS gate circuit 202 is made up of a PMOS transistor having a gate to which the program clock signal PCK is input and an NMOS transistor having a gate to which an inversion signal NCK of the program clock signal PCK is input. A program enable transmission signal PAmT (i−1) generated by the (i−1)th shift register is input to the first CMOS gate circuit 202. A program control signal FPGI is input to the first CMOS gate circuit 202 in the first-stage shift register.
A signal from the first CMOS gate circuit 202 is input to the first inverter circuit 203. A signal from the first inverter circuit 203 is input to the first tri-state inverter circuit 204, which then inverts the input signal and inputs the resultant signal to the connection between the first CMOS gate circuit 202 and the first inverter circuit 203. The program clock signal PCK is input to a control terminal of the first tri-state inverter circuit 204 as a control signal (which performs an enabling operation when at the H level).
The second CMOS gate circuit 205 is made up of a PMOS transistor having a gate to which the inversion signal NCK of the program clock signal PCK is input and an NMOS transistor having a gate to which the program clock signal PCK is input. The signal from the first inverter circuit 203 is input to the second CMOS gate circuit 205.
A signal from the second CMOS gate circuit 205 is input to the second inverter circuit 206, which then inverts the input signal to generate a program enable transmission signal PAmTi and also generates the program enable signal PBmTi.
A signal from the second inverter circuit 206 is input to the second tri-state inverter circuit 207, which then inverts the input signal and inputs the resultant signal to the connection between the second CMOS gate circuit 205 and the second inverter circuit 206. Furthermore, the inversion signal NCK of the program clock signal PCK is input to a control terminal of the second tri-state inverter circuit 207 as a control signal (which performs an enabling operation when at the H level).
The operation of the electric fuse circuit configured as described above will be described below with reference to FIG. 13. FIG. 13 is a waveform diagram showing the operation of the conventional electric fuse circuit.
First, the operation of the ith-stage electric fuse core 400 will be described.
For programming, first, the program data signal FBmTi to be input to one of the two input terminals of the AND circuit 403 in the electric fuse core 400 is set to the H level or a Low level (hereinafter referred to as an L level). Specifically, the program data signal FBmTi is set to the H level to set the electric fuse element to a fused state and to the L level to set the electric fuse element to a non-fused state.
The program enable signal PBmTi is input to the other input terminal of the AND circuit 403 in the electric fuse core 400. The electric fuse core 400 can keep the electric fuse element 401 in the fused state only while the program enable signal PBmTi is at the H level. That is, if the program data signal FBmTi is at the H level, the program signal INmTi generated by the AND circuit 403 remains at the H level while the program enable signal PBmTi is at the H level. In this state, the NMOS transistor 402 is on to pass a current through the electric fuse element 401 to set the electric fuse element to the fused state. On the other hand, if the program data signal FBmTi is at the L level, the program signal INmTi remains at the L level even when the program enable signal PBmTi switches to the H level. The NMOS transistor 402 thus remains off to prevent a current from flowing through the electric fuse element 401. This in turn prevents the electric fuse element 401 from entering the fused state (non-fused state).
Now, the operation of the whole electric fuse circuit will be described.
For example, to program the n electric fuse cores 400 so that the cores 400 have data 1, 0, . . . , 1 in this order, first, the signal levels of the program data signals FBmT1, FBmT2, . . . , and FBmTn are set to H, L, . . . , and H in this order.
Then, the program control signal FPGI to be input to the first stage of the program shift register block 200 is raised from the L level to the H level with sufficient setup maintained for the rising edge of the program clock signal PCK. At this time, since the signal PCK is at the L level, the first CMOS gate circuit 202 (see FIG. 12) is on. While the signal PCK is at the L level, the signal FPGI of the H level is input to the first-stage shift register 201.
When the signal PCK rises from the L level to the H level, the first CMOS gate circuit 202 is turned off. The first inverter circuit 203 and first tri-state inverter circuit 204 in the first-stage shift register 201 latch the signal (L level) from the first inverter circuit 203. At the same time, the second CMOS gate circuit 205 is turned on to switch the program enable signal PBmT1 and program enable transmission signal PAmT1 generated by the first-stage shift register 201 to the H level. The signal FPGI is dropped to the L level while the signal PCK is at the H level.
Then, when the signal PCK rises from the H level to the L level, the first CMOS gate circuit 202 is turned on to input the signal FPGI of the L level to the first-stage shift register 201. At the same time, the second CMOS gate circuit 205 is turned off, and the second inverter circuit 206 and second tri-state inverter circuit 207 in the first-stage shift register 201 latch the signal (H level) from the second inverter circuit 206. The latch operation maintains the program enable signal PBmT1 and program enable transmission signal PAmT1 generated by the first-stage shift register 201, at the H level. Furthermore, while the signal PCK is at the L level, the program enable transmission signal PAmT1 of the H level is input to the second-stage shift register 201.
Such an operation of the program shift register block 200 allow the program enable signal PBmTi (i=1 to n) and program enable transmission signal PAmTi (i=1 to n) having a width equal to one period of the signal PCK to be sequentially generated every time the program clock signal PCK repeats a periodic clock operation.
When the program enable signal PBmTi (i=1 to n) input to the AND circuit 403 switches to the H level, the electric fuse core 400 programs the electric fuse element 401. That is, the state of the program signal INmTi (i=1 to n) generated by the AND circuit 403 is sequentially determined at each rising edge of the signal PCK in accordance with the program data signal (FBmT1, FBmT2, . . . , FBmTn)=(H, L, . . . , H).
In the example shown in FIG. 13, when the program enable signal PBmT1 from the first-stage shift register 201 switches to the H level, the program signal INmT1 generated by the AND circuit 403 in the first-stage electric fuse core 400 switches to the H level. During the period corresponding to the pulse width of the signal PCK, the NMOS transistor 402 is on and the first-stage electric fuse element 401 is in the fused state. On the other hand, even when the program enable signal PBmT2 from the second-stage shift register 201 switches to the H level, the program signal INmT2 generated by the AND circuit 403 in the second-stage electric fuse core 400 remains at the L level. The NMOS transistor 402 remains off state and the second-stage electric fuse element 401 is in the non-fused state instead of the fused state. Although not shown in the drawings, as in the case of the second stage, the third- to (n−1)th-stage electric fuse elements 401 are in the non-fused state. Furthermore, when the program enable signal PBmTn from the final-stage shift register 201 switches to the H level, the final-stage electric fuse element 401 is set to the fused state as in the case of the first-stage electric fuse element 401.
The program enable signal PBmTi (i=1 to n) with the one pulse waveform transferred by the program shift register block is thus used to program the electric fuse elements one by one. This enables programming using the existing general-purpose tester. Furthermore, the serial connection of the shift registers allows the circuit to be configured with a small number of terminals. This enables the implementation of an electric fuse circuit that can be mounted in a system LSI.
However, with the conventional electric fuse circuit, if for example, the electric fuse element has a resistance value of 120Ω and a current of about 20 mA is fed to set the electric fuse element to the fused state, a voltage of at least 2.4 V needs to be applied across the electric fuse element. Thus, a 3.3 V_IO NMOS transistor has been used to apply a voltage of about 3 V to the electric fuse element. The conventional electric fuse circuit thus requires a large-sized 3.3 V_IO NMOS transistor having a gate width W of about 60 μm as a switch transistor allowing the feeding of a current required to set the electric fuse element to the fused state. Furthermore, the 3.3 V_IO transistor is also used for an input line to the gate of the NMOS transistor, increasing the area of the electric fuse circuit (the area of the 3.3 V_IO transistor is almost double that of a 1.2 V_logic transistor). In particular, with the possible advancement of fine-pattern processes in the future, the yield of memory cells is expected to decrease to further increase the number of electric fuse elements mounted. Consequently, the area of the electric fuse circuit is expected to be of interest.
Thus, in the conventional electric fuse circuit shown in FIG. 11, the 1.2 V_logic transistor can be used as the NMOS transistor 402. However, in the conventional electric fuse circuit, whenever the gate voltage of the NMOS transistor 402 is ‘0’ V, the same voltage (about 3.3 V) as applied to the top of the electric fuse element 401 is applied to a drain of the NMOS transistor 402, resulting in a potential difference of about 3.3 V between the gate and drain of the NMOS transistor 402. Thus, disadvantageously, TDDB degradation progresses.
On the other hand, in recent years, the use of OTP memories has been prevailing. The use of the OTP memory is likely to spread to various applications, for example, system LSI chips having an ID function for allowing system settings inherent in equipment to be recorded therein or a secure ID function for protecting information, semiconductor chips in each of which a lot number, a chip coordinate position, the results of inspections during a shipping process, and the like are recorded, to provide a chip ID function for enabling tracing such as failure analysis, and IC tags intended for tracking such as distribution management or identification of aircraft luggage.
An OTP memory of a middle capacity of about 1 to 10 kbits is used for the above-described applications. Furthermore, since the above-described chips and tags are mass-produced, the OTP memory for these applications has to be manufactured inexpensively enough to avoid affecting the initial costs of the products, service costs, and the like.
Additionally, to be mixed into a system LSI for an advanced process, the OTP memory must be based on logics similarly to SRAMs or ROMs and successfully developed on time. In spite of the possibility of a rewriting operation, a nonvolatile memory which requires a separate process similarly to flash memories and which is likely to be developed behind the most advanced process by several generations cannot meet the needs utilizing the most advanced process, in view of timing for the introduction, manufacturing costs, and the like.
The electric fuse circuit utilizing the silicide may be used as an OTP memory suitable for the above-described needs. The electric fuse circuit does not require a separate process as used for flash memories because of the use of the fusion of the silicide layer on the polysilicon layer. The electric fuse circuit can also be designed on the basis of logics.
However, as previously described, the configuration of the conventional electric fuse circuit disadvantageously has a great area impact on the chip, significantly affecting manufacturing costs.